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Expedition PCB - Pinnacle - Version 2009.0.369.456
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Job Directory:        D:\Job\Compulab\FM-LAN 2.0\PCB\

Design Status Report: D:\Job\Compulab\FM-LAN 2.0\PCB\LogFiles\DesignStatus_01.txt

Tue Jul 25 09:18:32 2017

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DESIGN STATUS
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Board Size Extents  ............ 97.48 X 48.22 (mm)
Route Border Extents  .......... 96.48 X 47.22 (mm)
Actual Board Area  ............. 3,465.3447 (mm)
Actual Route Area  ............. 3,309.5177 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    6,930.6894 Sq. (mm)1,236.2132 Sq. (mm)17.84 %

Pins  .......................... 422
Pins per Route Area  ........... .1275 Pins/Sq. (mm)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... .1143, .127, .1397, .254, .3048, .381, .508
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... None.
    Layer 5 is a Positive Plane Layer with nets
        3V3_S5
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... .1016, .1143, .127, .1397, .2032, .254, .3048, .381

Nets  .......................... 89
Connections  ................... 268
Open Connections  .............. 0
Differential Pairs  ............ 16
Differential Pair Names:   LAN0_MDIN0   LAN0_MDIP0
                           LAN0_MDIN1   LAN0_MDIP1
                           LAN0_MDIN2   LAN0_MDIP2
                           LAN0_MDIN3   LAN0_MDIP3
                           LAN1_MDIN0   LAN1_MDIP0
                           LAN1_MDIN1   LAN1_MDIP1
                           LAN1_MDIN2   LAN1_MDIP2
                           LAN1_MDIN3   LAN1_MDIP3
                           PCIE_LAN0_STXN   PCIE_LAN0_STXP
                           PCIE_LAN1_STXN   PCIE_LAN1_STXP
                           PCIE_REFCLK0_DN   PCIE_REFCLK0_DP
                           PCIE_REFCLK3_DN   PCIE_REFCLK3_DP
                           PCIE_RXN0_NGFF   PCIE_RXP0_NGFF
                           PCIE_RXN3_NGFF   PCIE_RXP3_NGFF
                           PCIE_TXN0_NGFF   PCIE_TXP0_NGFF
                           PCIE_TXN3_NGFF   PCIE_TXP3_NGFF
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 1,924.3119 (mm)

Trace Widths Used (mm)  ........ .1016, .1143, .127, .1397, .2032, .254, .3048, .381, .508
Vias  .......................... 149
Via Span  Name                   Quantity
   1-6    via20rd10_VPPS         18
          via20rd10              131

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 107
    Parts Mounted on Top  ...... 76
        SMD  ................... 64
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 11
    Parts Mounted on Bottom  ... 30
        SMD  ................... 30
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 1

Parts not Placed  .............. 0

Nested Cells  .................. 1
    U49-MO-229VCED-2
        Mechanical-PAD_60x55

Jumpers  ....................... 0

Through Holes  ................. 187
    Holes per Board Area  ...... .054 Holes/Sq. (mm)
Mounting Holes  ................ 7

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0