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xPCB Layout - Version 116.0.506.6156
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Job Directory:        D:\Job\Compulab VX.2\FC-OPLN\PCB\

Design Status Report: D:\Job\Compulab VX.2\FC-OPLN\PCB\LogFiles\DesignStatus_01.txt

Thu Aug 16 10:04:28 2018

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DESIGN STATUS
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Board Size Extents  ............ 61.303 X 97.477 (mm)
Route Border Extents  .......... 60.287 X 96.461 (mm)
Actual Board Area  ............. 5,068.072 (mm)
Actual Route Area  ............. 4,889.938 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    10,136.144 Sq. (mm)1,761.541 Sq. (mm)17.38 %

Pins  .......................... 589
Pins per Route Area  ........... 0.12 Pins/Sq. (mm)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 0.102, 0.114, 0.127, 0.152, 0.203, 0.229, 0.254, 0.305, 0.508
    Layer 2 is a Positive Plane Layer with nets
        GND
        CHASSIS
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        +3V3A
        +3V3S
        CHASSIS
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 0.102, 0.114, 0.127, 0.203, 0.254, 0.305, 0.33, 0.508

Nets  .......................... 114
Connections  ................... 398
Open Connections  .............. 0
Differential Pairs  ............ 12
Differential Pair Names:   LAN_SER_N   LAN_SER_P
                           LAN_SET_N   LAN_SET_P
                           PCIE0_CLKN   PCIE0_CLKP
                           PCIE0_RXN   PCIE0_RXP
                           PCIE0_TXN   PCIE0_TXP
                           PCIE3_CLKN   PCIE3_CLKP
                           PCIE3_RXN   PCIE3_RXP
                           PCIE3_RXN_C   PCIE3_RXP_C
                           PCIE3_TXN   PCIE3_TXP
                           SATA_RXN   SATA_RXP
                           SATA_TXN   SATA_TXP
                           USB_N   USB_P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 3,651.421 (mm)

Trace Widths Used (mm)  ........ 0.102, 0.114, 0.127, 0.152, 0.203, 0.229, 0.254, 0.305, 0.33, 0.508
Vias  .......................... 307
Via Span  Name                   Quantity
   1-4    018VIA8_sm             21
          018VIA8                286

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 104
    Parts Mounted on Top  ...... 18
        SMD  ................... 16
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 84
        SMD  ................... 84
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 2

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 337
    Holes per Board Area  ...... 0.066 Holes/Sq. (mm)
Mounting Holes  ................ 10

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0