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xPCB Layout - Version 116.0.576.0568
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Job Directory:        D:\work\Valigent\Temp\CM-203_FC-PCI_Rev2.0\PCB\

Design Status Report: D:\work\Valigent\Temp\CM-203_FC-PCI_Rev2.0\PCB\LogFiles\DesignStatus_00.txt

Thu Jan 03 14:02:19 2019

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DESIGN STATUS
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Board Size Extents  ............ 61.303 X 97.477 (mm)
Route Border Extents  .......... 60.591 X 96.77 (mm)
Actual Board Area  ............. 5,126.318 (mm)
Actual Route Area  ............. 5,001.865 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    10,252.637 Sq. (mm)2,039.06 Sq. (mm) 19.89 %

Pins  .......................... 523
Pins per Route Area  ........... 0.105 Pins/Sq. (mm)

Layers  ........................ 8
    Layer 1 is a signal layer
        Trace Widths  .......... 0.137, 0.14, 0.203, 0.254, 0.305
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 0.069, 0.097, 0.305
    Layer 4 is a signal layer
        Trace Widths  .......... None.
    Layer 5 is a signal layer
        Trace Widths  .......... 0.094, 0.119
    Layer 6 is a signal layer
        Trace Widths  .......... 0.094, 0.119
    Layer 7 is a Positive Plane Layer with nets
        VCC_3V3
        Trace Widths  .......... None.
    Layer 8 is a signal layer
        Trace Widths  .......... 0.137, 0.14, 0.203, 0.305, 0.508

Nets  .......................... 108
Connections  ................... 330
Open Connections  .............. 1
Differential Pairs  ............ 11
Differential Pair Names:   PCIE0_CLKN   PCIE0_CLKP
                           PCIE0_RXN   PCIE0_RXP
                           PCIE0_TXN   PCIE0_TXP
                           PCIE3_CLKN   PCIE3_CLKP
                           PCIE3_RXN   PCIE3_RXP
                           PCIE3_TXN   PCIE3_TXP
                           SATA_RXN   SATA_RXP
                           SATA_TXN   SATA_TXP
                           USB_UP_N   USB_UP_P
                           USB_1_N   USB_1_P
                           USB_2_N   USB_2_P
                           
Percent Routed  ................ 99.70 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 3,562.247 (mm)

Trace Widths Used (mm)  ........ 0.069, 0.094, 0.097, 0.119, 0.119, 0.137, 0.14, 0.203, 0.254, 0.305, 0.508
Vias  .......................... 366
Via Span  Name                   Quantity
   1-8    VIA18x8                360
          VIA18x8_VPCS           6

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 74
    Parts Mounted on Top  ...... 24
        SMD  ................... 23
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 1
    Parts Mounted on Bottom  ... 48
        SMD  ................... 47
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    Edge Connector Parts  ...... 2

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 375
    Holes per Board Area  ...... 0.073 Holes/Sq. (mm)
Mounting Holes  ................ 9
