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xPCB Layout - Version 116.0.506.6099
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Job Directory:        D:\Job\Compulab VX.2\FC-USB-v. 1.0\PCB\

Design Status Report: D:\Job\Compulab VX.2\FC-USB-v. 1.0\PCB\LogFiles\DesignStatus_05.txt

Thu Sep 28 06:47:52 2017

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DESIGN STATUS
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Board Size Extents  ............ 3.8378 X 1.7764 (in)
Route Border Extents  .......... 3.7906 X 1.7291 (in)
Actual Board Area  ............. 4.9949 (in)
Actual Route Area  ............. 4.7174 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    9.9898 Sq. (in)   1.2759 Sq. (in)   12.77 %

Pins  .......................... 279
Pins per Route Area  ........... 59.1424 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 4.6, 4.9, 10, 12, 20, 30
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 4.6, 4.9, 12, 20, 35

Nets  .......................... 55
Connections  ................... 189
Open Connections  .............. 0
Differential Pairs  ............ 9
Differential Pair Names:   USB_UP_N   USB_UP_P
                           USB_1FL_N   USB_1FL_P
                           USB_1_N   USB_1_P
                           USB_2FL_N   USB_2FL_P
                           USB_2_N   USB_2_P
                           USB_3FL_N   USB_3FL_P
                           USB_3_N   USB_3_P
                           USB_4FL_N   USB_4FL_P
                           USB_4_N   USB_4_P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 56.1921 (in)

Trace Widths Used (th)  ........ 4.6, 4.9, 10, 12, 20, 30, 35
Vias  .......................... 91
Via Span  Name                   Quantity
   1-4    VIA8_pad18             24
          via20rd10              67

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 70
    Parts Mounted on Top  ...... 68
        SMD  ................... 54
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 1
        SMD  ................... 1
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 1

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 124
    Holes per Board Area  ...... 24.8253 Holes/Sq. (in)
Mounting Holes  ................ 5

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0