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xPCB Layout - Version 116.0.506.6156
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Job Directory:        D:\Job\Compulab VX.2\FC-USB-v. 1.1\PCB\

Design Status Report: D:\Job\Compulab VX.2\FC-USB-v. 1.1\PCB\LogFiles\DesignStatus_08.txt

Wed Dec 12 14:39:51 2018

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DESIGN STATUS
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Board Size Extents  ............ 3.838 X 1.776 (in)
Route Border Extents  .......... 3.791 X 1.729 (in)
Actual Board Area  ............. 4.995 (in)
Actual Route Area  ............. 4.717 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    9.99 Sq. (in)     1.972 Sq. (in)    19.74 %

Pins  .......................... 530
Pins per Route Area  ........... 112.349 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 4.6, 4.9, 10, 12, 20, 30
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... 20
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 4.6, 4.9, 10, 12, 20, 35

Nets  .......................... 132
Connections  ................... 374
Open Connections  .............. 0
Differential Pairs  ............ 18
Differential Pair Names:   PCIE0_CLKN   PCIE0_CLKP
                           PCIE0_RXN   PCIE0_RXP
                           PCIE0_TXN   PCIE0_TXP
                           USB_A_3FL_N   USB_A_3FL_P
                           USB_A_4FL_N   USB_A_4FL_P
                           USB_A1_N   USB_A1_P
                           USB_A2_N   USB_A2_P
                           USB_A3_N   USB_A3_P
                           USB_A4_N   USB_A4_P
                           USB_B_1FL_N   USB_B_1FL_P
                           USB_B_2FL_N   USB_B_2FL_P
                           USB_B_3FL_N   USB_B_3FL_P
                           USB_B_4FL_N   USB_B_4FL_P
                           USB_B1_N   USB_B1_P
                           USB_B2_N   USB_B2_P
                           USB_B3_N   USB_B3_P
                           USB_B4_N   USB_B4_P
                           USB_UP_N   USB_UP_P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 117.382 (in)

Trace Widths Used (th)  ........ 4.6, 4.9, 10, 12, 20, 30, 35
Vias  .......................... 273
Via Span  Name                   Quantity
   1-4    VIA8_pad18             133
          via20rd10              140

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 123
    Parts Mounted on Top  ...... 71
        SMD  ................... 55
        Through  ............... 6
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 51
        SMD  ................... 51
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 1

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 315
    Holes per Board Area  ...... 63.064 Holes/Sq. (in)
Mounting Holes  ................ 6

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0