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xPCB Layout - Version 116.0.506.6156
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Job Directory:        D:\Compulab VX.2\TEL-MEDIA\PCB\

Design Status Report: D:\Compulab VX.2\TEL-MEDIA\PCB\LogFiles\DesignStatus_13.txt

Mon Sep 09 11:27:51 2019

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DESIGN STATUS
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Board Size Extents  ............ 1.75 X 1.9 (in)
Route Border Extents  .......... 1.74 X 1.86 (in)
Actual Board Area  ............. 3.27 (in)
Actual Route Area  ............. 3.13 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    6.55 Sq. (in)     1.41 Sq. (in)     21.55 %

Pins  .......................... 347
Pins per Route Area  ........... 110.85 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... None.
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... None.

Nets  .......................... 83
Connections  ................... 241
Open Connections  .............. 232
Differential Pairs  ............ 0
Percent Routed  ................ 3.73 %

Netline Length  ................ 27.83 (in)
Netline Manhattan Length  ...... 33.36 (in)
Total Trace Length  ............ 0 (in)

Trace Widths Used (th)  ........ None.
Vias  .......................... 0

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 90
    Parts Mounted on Top  ...... 90
        SMD  ................... 78
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 11
    Holes per Board Area  ...... 3.36 Holes/Sq. (in)
Mounting Holes  ................ 3

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0