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xPCB Layout - Version 116.0.506.6156
=======================================================================

Job Directory:        E:\Compulab VX.2\FT-LAN4\PCB\

Design Status Report: E:\Compulab VX.2\FT-LAN4\PCB\LogFiles\DesignStatus_01.txt

Thu Jul 16 08:15:42 2020

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DESIGN STATUS
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Board Size Extents  ............ 2.626 X 1.835 (in)
Route Border Extents  .......... 2.618 X 1.796 (in)
Actual Board Area  ............. 4.722 (in)
Actual Route Area  ............. 4.529 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    9.443 Sq. (in)    3.727 Sq. (in)    39.47 %

Pins  .......................... 961
Pins per Route Area  ........... 212.211 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 4.6, 4.8, 8, 10, 12, 14
    Layer 2 is a Positive Plane Layer with nets
        GND
        CHASSIS_ETH
        CHASSIS_ETH2
        Trace Widths  .......... 19.685, 20
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 4.6, 4.8, 8, 10, 12, 14, 19.685

Nets  .......................... 215
Connections  ................... 666
Open Connections  .............. 0
Differential Pairs  ............ 45
Differential Pair Names:   CLK_PCIE_N   CLK_PCIE_P
                           CLK_0N   CLK_0P
                           CLK_0N_C   CLK_0P_C
                           CLK_0N_R   CLK_0P_R
                           CLK_1N   CLK_1P
                           CLK_1N_C   CLK_1P_C
                           CLK_1N_R   CLK_1P_R
                           CLK_2N   CLK_2P
                           CLK_2N_C   CLK_2P_C
                           CLK_2N_R   CLK_2P_R
                           CLK_3N   CLK_3P
                           CLK_3N_C   CLK_3P_C
                           CLK_3N_R   CLK_3P_R
                           LAN1_MDI0N   LAN1_MDI0P
                           LAN1_MDI1N   LAN1_MDI1P
                           LAN1_MDI2N   LAN1_MDI2P
                           LAN1_MDI3N   LAN1_MDI3P
                           LAN2_MDI0N   LAN2_MDI0P
                           LAN2_MDI1N   LAN2_MDI1P
                           LAN2_MDI2N   LAN2_MDI2P
                           LAN2_MDI3N   LAN2_MDI3P
                           LAN3_MDI0N   LAN3_MDI0P
                           LAN3_MDI1N   LAN3_MDI1P
                           LAN3_MDI2N   LAN3_MDI2P
                           LAN3_MDI3N   LAN3_MDI3P
                           LAN4_MDI0N   LAN4_MDI0P
                           LAN4_MDI1N   LAN4_MDI1P
                           LAN4_MDI2N   LAN4_MDI2P
                           LAN4_MDI3N   LAN4_MDI3P
                           PCIE0_RXN   PCIE0_RXP
                           PCIE0_RXN_C   PCIE0_RXP_C
                           PCIE0_TXN   PCIE0_TXP
                           PCIE0_TXN_C   PCIE0_TXP_C
                           PCIE1_RXN   PCIE1_RXP
                           PCIE1_RXN_C   PCIE1_RXP_C
                           PCIE1_TXN   PCIE1_TXP
                           PCIE1_TXN_C   PCIE1_TXP_C
                           PCIE2_RXN   PCIE2_RXP
                           PCIE2_RXN_C   PCIE2_RXP_C
                           PCIE2_TXN   PCIE2_TXP
                           PCIE2_TXN_C   PCIE2_TXP_C
                           PCIE3_RXN   PCIE3_RXP
                           PCIE3_RXN_C   PCIE3_RXP_C
                           PCIE3_TXN   PCIE3_TXP
                           PCIE3_TXN_C   PCIE3_TXP_C
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 117.982 (in)

Trace Widths Used (th)  ........ 4.6, 4.8, 8, 10, 12, 14, 19.685, 20
Vias  .......................... 390
Via Span  Name                   Quantity
   1-4    VIA8_pad18             113
          via20rd10              187
          via20rd10_VPPS         90

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 253
    Parts Mounted on Top  ...... 119
        SMD  ................... 107
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 134
        SMD  ................... 134
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 460
    Holes per Board Area  ...... 97.422 Holes/Sq. (in)
Mounting Holes  ................ 12

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0