
                               Forward Annotation
                               ------------------

                        12:03 PM Monday, October 07, 2019
               Job Name: V:\Compulab VX.2\FT-USB4\PCB\FT-USB4.pcb


Version:  01.01.00

     The PDBs listed in the project file will be searched to satisfy the parts
      requirements of the iCDB only for parts not already found in the
      Target PDB.

     The schematic source is a Keyin Netlist.
     

     Netlist has no syntax errors

     The Keyin Netlist has been read

     Target PDB Name: Work\Layout_Temp\PartsDB.pdb

     Number of Part Numbers: 15
          Part Numb: 111S30801S -> Vend Part: 111S30801S 
          Part Numb: 124S97030S -> Vend Part: 124S97030S 
          Part Numb: 132D10070S -> Vend Part: 132D10070S 
          Part Numb: 142D11800S -> Vend Part: 142D11800S 
          Part Numb: 147D30000S -> Vend Part: 147D30000S 
          Part Numb: 151B10400S -> Vend Part: 151B10400S 
          Part Numb: 151B10600S -> Vend Part: 151B10600S 
          Part Numb: 151C224B0S -> Vend Part: 151C224B0S 
          Part Numb: 161C00005S -> Vend Part: 161C00005S 
          Part Numb: 161C10011S -> Vend Part: 161C10011S 
          Part Numb: 161C10021S -> Vend Part: 161C10021S 
          Part Numb: 161C63421S -> Vend Part: 161C63421S 
          Part Numb: 170I30100S -> Vend Part: 170I30100S 
          Part Numb: 180K00903 -> Vend Part: 180K00903 
          Part Numb: 182K06700S -> Vend Part: 182K06700S 

     Number of Part Names: 0

     Number of Part Labels: 0




     77 nets were found containing 305 pins
     81 components were found

     Creating a formatted Schematic Netlist (LogFiles\SchematicNetlist.txt)...
     A formatted Schematic Netlist has been created.

     The Logic DataBase and the Schematic Design are now in sync.  Use
      Netload to bring the Component Design into sync.

     Logic Data has been successfully Compiled with no errors or warnings.
      Please proceed with your component Design.
                                     NetLoad
                                     -------

                        12:03 PM Monday, October 07, 2019
               Job Name: V:\Compulab VX.2\FT-USB4\PCB\FT-USB4.pcb


Version:  02.11.12

	Netloading the Layout.  Unused components will be deleted.

	Unconnected pins will be set to net "(Net0)".

	Schematic reference designator changes will be forward annotated.


     Netload completed successfully with 0 warning(s).
     
     Back Annotating...

  Updating Logic Database...

     Version:  99.00.05

     Writing a list of routed plane pins to Logic\rtdplane.caf.

     Finished updating the Logic Database.

     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...
     A formatted Schematic Netlist has been created.

            Creating a new Keyin Netlist (V:\Compulab VX.2\FT-USB4\PCB\Logic\FT-USB4-24_09.kyn)
            from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
  A new Keyin Netlist has been generated.



                 Beginning Netload on the Layout Design.
           ---------------------------------------------------

Forward-Annotation on the Layout Design has been successfully completed.

There were 0 reassignments of nets.
There were 0 traces broken back.
There were 0 nets removed from the Layout Design.