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xPCB Layout - Version 116.0.506.6156
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Job Directory:        D:\Compulab VX.2\FT_USB2X4V\PCB\

Design Status Report: D:\Compulab VX.2\FT_USB2X4V\PCB\LogFiles\DesignStatus_00.txt

Tue Jul 07 08:22:47 2020

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DESIGN STATUS
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Board Size Extents  ............ 1.309 X 1.289 (in)
Route Border Extents  .......... 1.301 X 1.249 (in)
Actual Board Area  ............. 1.636 (in)
Actual Route Area  ............. 1.533 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    3.272 Sq. (in)    1.382 Sq. (in)    42.23 %

Pins  .......................... 341
Pins per Route Area  ........... 222.491 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 4.5, 12, 20, 24, 25
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 4.5, 4.6, 8, 12, 20

Nets  .......................... 58
Connections  ................... 251
Open Connections  .............. 114
Differential Pairs  ............ 9
Differential Pair Names:   HUBUSB1_DN   HUBUSB1_DP
                           HUBUSB2_DN   HUBUSB2_DP
                           HUBUSB3_DN   HUBUSB3_DP
                           HUBUSB4_DN   HUBUSB4_DP
                           USB_CN1_DN   USB_CN1_DP
                           USB_CN2_DN   USB_CN2_DP
                           USB_CN3_DN   USB_CN3_DP
                           USB_CN4_DN   USB_CN4_DP
                           USB2_N   USB2_P
                           
Percent Routed  ................ 54.58 %

Netline Length  ................ 12.665 (in)
Netline Manhattan Length  ...... 15.139 (in)
Total Trace Length  ............ 14.976 (in)

Trace Widths Used (th)  ........ 4.5, 4.6, 8, 12, 20, 24, 25
Vias  .......................... 68
Via Span  Name                   Quantity
   1-4    via20rd10              14
          via18rd8               54

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 102
    Parts Mounted on Top  ...... 36
        SMD  ................... 21
        Through  ............... 6
        Test Points  ........... 0
        Mechanical  ............ 9
    Parts Mounted on Bottom  ... 66
        SMD  ................... 66
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 102
    Holes per Board Area  ...... 62.344 Holes/Sq. (in)
Mounting Holes  ................ 4
