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xPCB Layout - Version 116.0.506.6156
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Job Directory:        E:\Compulab VX.2\FT_USB2X4V\PCB\

Design Status Report: E:\Compulab VX.2\FT_USB2X4V\PCB\LogFiles\DesignStatus_04.txt

Mon Jul 27 09:33:04 2020

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DESIGN STATUS
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Board Size Extents  ............ 33.261 X 32.742 (mm)
Route Border Extents  .......... 33.05 X 31.72 (mm)
Actual Board Area  ............. 1,055.544 (mm)
Actual Route Area  ............. 988.804 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    2,111.088 Sq. (mm)997.414 Sq. (mm)  47.25 %

Pins  .......................... 340
Pins per Route Area  ........... 0.344 Pins/Sq. (mm)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 0.114, 0.254, 0.305, 0.508
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        +5VA
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 0.114, 0.203, 0.305, 0.508

Nets  .......................... 58
Connections  ................... 255
Open Connections  .............. 0
Differential Pairs  ............ 9
Differential Pair Names:   HUBUSB1_DN   HUBUSB1_DP
                           HUBUSB2_DN   HUBUSB2_DP
                           HUBUSB3_DN   HUBUSB3_DP
                           HUBUSB4_DN   HUBUSB4_DP
                           USB_CN1_DN   USB_CN1_DP
                           USB_CN2_DN   USB_CN2_DP
                           USB_CN3_DN   USB_CN3_DP
                           USB_CN4_DN   USB_CN4_DP
                           USB2_N   USB2_P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 740.444 (mm)

Trace Widths Used (mm)  ........ 0.114, 0.203, 0.254, 0.305, 0.508
Vias  .......................... 105
Via Span  Name                   Quantity
   1-4    via20rd10              13
          via18rd8               92

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 93
    Parts Mounted on Top  ...... 27
        SMD  ................... 20
        Through  ............... 6
        Test Points  ........... 0
        Mechanical  ............ 1
    Parts Mounted on Bottom  ... 66
        SMD  ................... 66
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 139
    Holes per Board Area  ...... 0.132 Holes/Sq. (mm)
Mounting Holes  ................ 4

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0