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xPCB Layout - Version 116.0.506.6156
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Job Directory:        D:\Compulab VX.2\FT-NVMEM2\PCB\

Design Status Report: D:\Compulab VX.2\FT-NVMEM2\PCB\LogFiles\DesignStatus_02.txt

Wed Oct 16 09:33:08 2019

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DESIGN STATUS
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Board Size Extents  ............ 0.87 X 8.61 (in)
Route Border Extents  .......... 0.86 X 8.6 (in)
Actual Board Area  ............. 7.45 (in)
Actual Route Area  ............. 7.42 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    14.91 Sq. (in)    0.55 Sq. (in)     3.71 %

Pins  .......................... 189
Pins per Route Area  ........... 25.48 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 4, 8, 11.85
    Layer 2 is a signal layer
        Trace Widths  .......... 1.85, 1.89, 2, 2.37, 4
    Layer 3 is a signal layer
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 4, 8, 10, 11.85, 12

Nets  .......................... 39
Connections  ................... 111
Open Connections  .............. 0
Differential Pairs  ............ 13
Differential Pair Names:   PCIE_CLKN   PCIE_CLKP
                           PCIE_RX0N   PCIE_RX0P
                           PCIE_RX1N   PCIE_RX1P
                           PCIE_RX2N   PCIE_RX2P
                           PCIE_RX3N   PCIE_RX3P
                           PCIE_TX0N   PCIE_TX0P
                           PCIE_TX0N_C   PCIE_TX0P_C
                           PCIE_TX1N   PCIE_TX1P
                           PCIE_TX1N_C   PCIE_TX1P_C
                           PCIE_TX2N   PCIE_TX2P
                           PCIE_TX2N_C   PCIE_TX2P_C
                           PCIE_TX3N   PCIE_TX3P
                           PCIE_TX3N_C   PCIE_TX3P_C
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 197.61 (in)

Trace Widths Used (th)  ........ 1.85, 1.89, 2, 2.37, 4, 8, 10, 11.85, 12
Vias  .......................... 128
Via Span  Name                   Quantity
   1-4    VIA8_pad16             128

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 25
    Parts Mounted on Top  ...... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 24
        SMD  ................... 24
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 1

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 132
    Holes per Board Area  ...... 17.71 Holes/Sq. (in)
Mounting Holes  ................ 4

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0