
                               Forward Annotation
                               ------------------

                     10:28 AM Wednesday, September 25, 2019
           Job Name: D:\Compulab VX.2\TEL-RIBNVME\PCB\TEL-RIBNVME.pcb


Version:  01.01.00

     The PDBs listed in the project file will be searched to satisfy the parts
      requirements of the iCDB only for parts not already found in the
      Target PDB.

     The schematic source is a Keyin Netlist.
     

    2:  no valid page assigned previous to %%part/value - assuming page 1
   28:  no valid priority assigned previous to %%net - assuming priority 6
     Netlist has no syntax errors

     The Keyin Netlist has been read

     Target PDB Name: Work\Layout_Temp\PartsDB.pdb

     Number of Part Numbers: 9
          Part Numb: NA1 -> Vend Part: NA1 
          Part Numb: 111S30801S -> Vend Part: 111S30801S 
          Part Numb: 151B10400S -> Vend Part: 151B10400S 
          Part Numb: 151B10600S -> Vend Part: 151B10600S 
          Part Numb: 151C22400S -> Vend Part: 151C22400S 
          Part Numb: 161C00005S -> Vend Part: 161C00005S 
          Part Numb: 161C10011S -> Vend Part: 161C10011S 
          Part Numb: 161C10021S -> Vend Part: 161C10021S 
          Part Numb: 182K06706S -> Vend Part: 182K06706S 

     Number of Part Names: 0

     Number of Part Labels: 0




     39 nets were found containing 140 pins
     25 components were found

     Creating a formatted Schematic Netlist (LogFiles\SchematicNetlist.txt)...
     A formatted Schematic Netlist has been created.

     The Logic DataBase and the Schematic Design are now in sync.  Use
      Netload to bring the Component Design into sync.

     Logic Data has been successfully Compiled with no errors or warnings.
      Please proceed with your component Design.
                                     NetLoad
                                     -------

                     10:28 AM Wednesday, September 25, 2019
           Job Name: D:\Compulab VX.2\TEL-RIBNVME\PCB\TEL-RIBNVME.pcb


Version:  02.11.12

	Netloading the Layout.  Unused components will be deleted.

	Unconnected pins will be set to net "(Net0)".

	Schematic reference designator changes will be forward annotated.


    WARNING:  Removing PCB Net Name "RSVD_DIFF2_N" from the NetPropsDB.  It is no longer in the schematic.

    WARNING:  Removing PCB Net Name "RSVD_DIFF2_P" from the NetPropsDB.  It is no longer in the schematic.

 WARNING:  The pin order is being removed from net "PCIE_RX0N" because
  pin "P3-41" is no longer on this net in the LogicDB.

 WARNING:  The pin order is being removed from net "PCIE_RX0P" because
  pin "P3-43" is no longer on this net in the LogicDB.

     Netload completed successfully with 4 warning(s).
     
     Back Annotating...

  Updating Logic Database...

     Version:  99.00.05

     Writing a list of routed plane pins to Logic\rtdplane.caf.

     Finished updating the Logic Database.

     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...
     A formatted Schematic Netlist has been created.

            Creating a new Keyin Netlist (D:\Compulab VX.2\TEL-RIBNVME\PCB\Logic\TEL-RIBNVME-25_09.kyn)
            from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
  A new Keyin Netlist has been generated.



                 Beginning Netload on the Layout Design.
           ---------------------------------------------------
	Unresolvable short found at point (62145000, 1498000).
	Unresolvable short found at point (62145000, 1498000).
	Assigned net (Net0) to a via which was originally on net RSVD_DIFF2_N.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_N.
	Unresolvable short found at point (56896000, 5334000).
	Unresolvable short found at point (56896000, 5334000).
	Unresolvable short found at point (56645000, 1498000).
	Unresolvable short found at point (56645000, 1498000).
	Assigned net PCIE_RX0P to a trace which was originally on net PCIE_RX0N.
	Assigned net PCIE_RX0P to a trace which was originally on net PCIE_RX0N.
	Assigned net PCIE_RX0P to a via which was originally on net PCIE_RX0N.
	Assigned net PCIE_RX0P to a trace which was originally on net PCIE_RX0N.
	Unresolvable short found at point (59730900, 191984315).
	Unresolvable short found at point (59730900, 191984315).
	Assigned net PCIE_RX0N to a trace which was originally on net PCIE_RX0P.
	Assigned net PCIE_RX0N to a via which was originally on net PCIE_RX0P.
	Assigned net PCIE_RX0N to a trace which was originally on net PCIE_RX0P.
	Assigned net PCIE_RX0N to a trace which was originally on net PCIE_RX0P.
	Unresolvable short found at point (59900693, 189966600).
	Unresolvable short found at point (59900693, 189966600).
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_N.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_N.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_N.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_N.

=====================================================================
Assigned everything on net RSVD_DIFF2_N, which has no pins, to (Net0).
=====================================================================

	Assigned net (Net0) to a via which was originally on net RSVD_DIFF2_P.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_P.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_P.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_P.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_P.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_P.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_P.
	Assigned net (Net0) to a trace which was originally on net RSVD_DIFF2_P.

=====================================================================
Assigned everything on net RSVD_DIFF2_P, which has no pins, to (Net0).
=====================================================================


Some nets were completely deleted from the Layout Design....
	Deleted net RSVD_DIFF2_N, which has no pins, from the Layout Design.
	Deleted net RSVD_DIFF2_P, which has no pins, from the Layout Design.

Forward-Annotation on the Layout Design has been successfully completed.

There were 22 reassignments of nets.
There were 0 traces broken back.
There were 2 nets removed from the Layout Design.