=======================================================================
xPCB Layout - Version 116.0.506.6156
=======================================================================

Job Directory:        D:\Compulab VX.2\FT.G-DPLAN\PCB\

Design Status Report: D:\Compulab VX.2\FT.G-DPLAN\PCB\LogFiles\DesignStatus_00.txt

Wed Oct 23 08:51:02 2019

=======================================================================
DESIGN STATUS
=======================================================================
Board Size Extents  ............ 44.4 X 56.3 (mm)
Route Border Extents  .......... 44.37 X 55.3 (mm)
Actual Board Area  ............. 2,466.6 (mm)
Actual Route Area  ............. 2,366.99 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    4,933.2 Sq. (mm)  1,233.28 Sq. (mm) 25.00 %

Pins  .......................... 432
Pins per Route Area  ........... 0.18 Pins/Sq. (mm)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 0.12, 0.12, 0.2, 0.25, 0.3, 0.51
    Layer 2 is a Positive Plane Layer with nets
        GND
        CHASSIS_ETH
        CHASSIS
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        +3V3LAN
        +5VA
        Trace Widths  .......... None.
    Layer 4 is a Positive Plane Layer with nets
        +3V3S
        +1V5LAN
        +0V9LAN
        Trace Widths  .......... None.
    Layer 5 is a Positive Plane Layer with nets
        GND
        CHASSIS_ETH
        CHASSIS
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 0.1, 0.12, 0.12, 0.2, 0.3, 0.51

Nets  .......................... 101
Connections  ................... 316
Open Connections  .............. 0
Differential Pairs  ............ 23
Differential Pair Names:   AUXN_DATA   AUXP_CLK
                           CLK_PCIE_0N   CLK_PCIE_0P
                           DDI1_TX0N   DDI1_TX0P
                           DDI1_TX0N_C   DDI1_TX0P_C
                           DDI1_TX0N_CF   DDI1_TX0P_CF
                           DDI1_TX1N   DDI1_TX1P
                           DDI1_TX1N_C   DDI1_TX1P_C
                           DDI1_TX1N_CF   DDI1_TX1P_CF
                           DDI1_TX2N   DDI1_TX2P
                           DDI1_TX2N_C   DDI1_TX2P_C
                           DDI1_TX2N_CF   DDI1_TX2P_CF
                           DDI1_TX3N   DDI1_TX3P
                           DDI1_TX3N_C   DDI1_TX3P_C
                           DDI1_TX3N_CF   DDI1_TX3P_CF
                           LAN_MDI0N   LAN_MDI0P
                           LAN_MDI1N   LAN_MDI1P
                           LAN_MDI2N   LAN_MDI2P
                           LAN_MDI3N   LAN_MDI3P
                           PCIE2_RXN   PCIE2_RXP
                           PCIE2_RXN_C   PCIE2_RXP_C
                           PCIE2_TXN   PCIE2_TXP
                           PCIE2_TXN_C   PCIE2_TXP_C
                           USB2_2N   USB2_2P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 1,392.26 (mm)

Trace Widths Used (mm)  ........ 0.1, 0.12, 0.12, 0.2, 0.25, 0.3, 0.51
Vias  .......................... 219
Via Span  Name                   Quantity
   1-6    via18rd8_sm-top-bot    14
          via20rd10              132
          via18rd8               73

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 111
    Parts Mounted on Top  ...... 78
        SMD  ................... 67
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 9
    Parts Mounted on Bottom  ... 33
        SMD  ................... 33
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 246
    Holes per Board Area  ...... 0.1 Holes/Sq. (mm)
Mounting Holes  ................ 7

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0