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xPCB Layout - Version 116.0.506.6156
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Job Directory:        E:\Compulab VX.2\FT-SER4_V1.1\PCB\

Design Status Report: E:\Compulab VX.2\FT-SER4_V1.1\PCB\LogFiles\DesignStatus_03.txt

Thu Aug 13 16:04:16 2020

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DESIGN STATUS
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Board Size Extents  ............ 33.25 X 41.854 (mm)
Route Border Extents  .......... 33.05 X 40.838 (mm)
Actual Board Area  ............. 1,352.651 (mm)
Actual Route Area  ............. 1,277.924 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    2,705.302 Sq. (mm)1,912.235 Sq. (mm)70.68 %

Pins  .......................... 845
Pins per Route Area  ........... 0.661 Pins/Sq. (mm)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 0.107, 0.114, 0.135, 0.203, 0.254, 0.457
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 0.127
    Layer 4 is a signal layer
        Trace Widths  .......... 0.127, 0.508
    Layer 5 is a Positive Plane Layer with nets
        +3V3S
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 0.107, 0.114, 0.178, 0.203, 0.254, 0.457

Nets  .......................... 186
Connections  ................... 574
Open Connections  .............. 0
Differential Pairs  ............ 1
Differential Pair Names:   USB2N   USB2P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 3,243.629 (mm)

Trace Widths Used (mm)  ........ 0.107, 0.114, 0.127, 0.135, 0.178, 0.203, 0.254, 0.457, 0.508
Vias  .......................... 362
Via Span  Name                   Quantity
   1-6    018VIA_sm top,bot      5
          VIA8_pad18_sm top,bott 4
          VIA8_pad18             353

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 215
    Parts Mounted on Top  ...... 102
        SMD  ................... 85
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 16
    Parts Mounted on Bottom  ... 113
        SMD  ................... 113
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 370
    Holes per Board Area  ...... 0.274 Holes/Sq. (mm)
Mounting Holes  ................ 6

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0