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xPCB Layout - Version 116.0.506.6156
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Job Directory:        E:\Compulab\FT-SER4-09\PCB\

Design Status Report: E:\Compulab\FT-SER4-09\PCB\LogFiles\DesignStatus_00.txt

Mon Dec 23 09:25:54 2019

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DESIGN STATUS
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Board Size Extents  ............ 33.25 X 42.75 (mm)
Route Border Extents  .......... 33.05 X 41.75 (mm)
Actual Board Area  ............. 1,388.27 (mm)
Actual Route Area  ............. 1,312.75 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    2,776.53 Sq. (mm) 1,490.04 Sq. (mm) 53.67 %

Pins  .......................... 718
Pins per Route Area  ........... 0.55 Pins/Sq. (mm)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 0.12, 0.14, 0.18, 0.2, 0.25, 0.3, 0.38, 0.46
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 0.2
    Layer 4 is a signal layer
        Trace Widths  .......... 0.2
    Layer 5 is a Positive Plane Layer with nets
        +3V3S
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 0.14, 0.18, 0.2, 0.25, 0.3, 0.46, 0.51

Nets  .......................... 169
Connections  ................... 470
Open Connections  .............. 0
Differential Pairs  ............ 1
Differential Pair Names:   USB2N   USB2P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 2,916.2 (mm)

Trace Widths Used (mm)  ........ 0.12, 0.14, 0.18, 0.2, 0.25, 0.3, 0.38, 0.46, 0.51
Vias  .......................... 352
Via Span  Name                   Quantity
   1-6    via20rd10_VPPS         1
          VIA8_pad18             231
          via20rd10              120

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 154
    Parts Mounted on Top  ...... 79
        SMD  ................... 68
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 75
        SMD  ................... 75
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 360
    Holes per Board Area  ...... 0.26 Holes/Sq. (mm)
Mounting Holes  ................ 6
