=======================================================================
Xpedition Layout - Version 117.0.761.1122
=======================================================================

Job Directory:        E:\Compulab\FT-SER4-09\PCB\

Design Status Report: E:\Compulab\FT-SER4-09\PCB\LogFiles\DesignStatus_01.txt

Wed Feb 05 09:01:04 2020

=======================================================================
DESIGN STATUS
=======================================================================
Board Size Extents  ............ 1.309 X 1.648 (in)
Route Border Extents  .......... 1.301 X 1.608 (in)
Actual Board Area  ............. 2.097 (in)
Actual Route Area  ............. 1.981 (in)

Placement Areas: Name             Available         Required          Required/Available
                 Entire Board     4.193 Sq. (in)    2.378 Sq. (in)    56.71 %

Pins  .......................... 762
Pins per Route Area  ........... 384.696 Pins/Sq. (in)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 4.6, 5.6, 7, 8, 9.843, 10, 12, 15, 18
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 8
    Layer 4 is a signal layer
        Trace Widths  .......... 8
    Layer 5 is a Positive Plane Layer with nets
        +3V3S
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 5.6, 7, 8, 10, 12, 18, 20

Nets  .......................... 177
Connections  ................... 503
Open Connections  .............. 0
Differential Pairs  ............ 1
Differential Pair Names:   USB2N   USB2P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 116.683 (in)

Trace Widths Used (th)  ........ 4.6, 5.6, 7, 8, 9.843, 10, 12, 15, 18, 20
Vias  .......................... 369
Via Span  Name                   Quantity
   1-6    via20rd10_VPPS         43
          via20rd10              89
          VIA8_pad18             237

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 166
    Parts Mounted on Top  ...... 81
        SMD  ................... 70
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 85
        SMD  ................... 85
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 377
    Holes per Board Area  ...... 179.814 Holes/Sq. (in)
Mounting Holes  ................ 6

Wirebonds
    Bond Fingers ............... 0
    Bond Wires ................. 0