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xPCB Layout - Version 116.0.506.6156
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Job Directory:        E:\Compulab\FT-M2E\PCB\

Design Status Report: E:\Compulab\FT-M2E\PCB\LogFiles\DesignStatus_00.txt

Thu Jan 23 14:11:02 2020

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DESIGN STATUS
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Board Size Extents  ............ 0.866 X 0.958 (in)
Route Border Extents  .......... 0.827 X 0.916 (in)
Actual Board Area  ............. 0.83 (in)
Actual Route Area  ............. 0.757 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    1.659 Sq. (in)    0.774 Sq. (in)    46.67 %

Pins  .......................... 245
Pins per Route Area  ........... 323.597 Pins/Sq. (in)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 4.6, 4.8, 7, 8, 10, 12, 15
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... 20
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... 20, 40
    Layer 4 is a signal layer
        Trace Widths  .......... 4.6, 4.8, 8, 10, 15

Nets  .......................... 38
Connections  ................... 155
Open Connections  .............. 2
Differential Pairs  ............ 4
Differential Pair Names:   CLK_PCIE_N   CLK_PCIE_P
                           PCIE0_RXN   PCIE0_RXP
                           PCIE0_TXN   PCIE0_TXP
                           PCIE0_TXN_C   PCIE0_TXP_C
                           
Percent Routed  ................ 98.71 %

Netline Length  ................ 1.228 (in)
Netline Manhattan Length  ...... 1.513 (in)
Total Trace Length  ............ 19.733 (in)

Trace Widths Used (th)  ........ 4.6, 4.8, 7, 8, 10, 12, 15, 20, 40
Vias  .......................... 99
Via Span  Name                   Quantity
   1-4    VIA8_pad18_sm top,bott 5
          VIA8_pad18             94

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 57
    Parts Mounted on Top  ...... 50
        SMD  ................... 40
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 7
        SMD  ................... 7
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 107
    Holes per Board Area  ...... 128.969 Holes/Sq. (in)
Mounting Holes  ................ 8
