=======================================================================
xPCB Layout - Version 116.0.506.6156
=======================================================================

Job Directory:        E:\Compulab VX.2\FT-PCIEMINI Rev 1.1\PCB\

Design Status Report: E:\Compulab VX.2\FT-PCIEMINI Rev 1.1\PCB\LogFiles\DesignStatus_01.txt

Wed May 06 12:42:26 2020

=======================================================================
DESIGN STATUS
=======================================================================
Board Size Extents  ............ 33.25 X 69.628 (mm)
Route Border Extents  .......... 32.234 X 68.612 (mm)
Actual Board Area  ............. 2,154.867 (mm)
Actual Route Area  ............. 2,050.833 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    4,309.733 Sq. (mm)2,357.558 Sq. (mm)54.70 %

Pins  .......................... 304
Pins per Route Area  ........... 0.148 Pins/Sq. (mm)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 0.117, 0.122, 0.203, 0.305, 0.381
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 0.117, 0.122, 0.203, 0.305, 0.381

Nets  .......................... 46
Connections  ................... 216
Open Connections  .............. 0
Differential Pairs  ............ 6
Differential Pair Names:   CLK_PCIE_N   CLK_PCIE_P
                           PCIE0_RXN   PCIE0_RXP
                           PCIE0_RXN_R   PCIE0_RXP_R
                           PCIE0_TXN   PCIE0_TXP
                           PCIE0_TXN_R   PCIE0_TXP_R
                           USB2_N   USB2_P
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 938.928 (mm)

Trace Widths Used (mm)  ........ 0.117, 0.122, 0.203, 0.305, 0.381
Vias  .......................... 238
Via Span  Name                   Quantity
   1-4    VIA8_pad18_sm top,bott 10
          VIA8_pad18             228

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 79
    Parts Mounted on Top  ...... 23
        SMD  ................... 12
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 56
        SMD  ................... 56
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 2

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 250
    Holes per Board Area  ...... 0.116 Holes/Sq. (mm)
Mounting Holes  ................ 12

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0