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Xpedition Layout - Version 117.0.761.1122
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Job Directory:        D:\Compulab VX.2\FT.O-POW12\PCB\

Design Status Report: D:\Compulab VX.2\FT.O-POW12\PCB\LogFiles\DesignStatus_00.txt

Thu Jan 23 08:44:29 2020

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DESIGN STATUS
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Board Size Extents  ............ 13.65 X 26.38 (mm)
Route Border Extents  .......... 13.65 X 26.38 (mm)
Actual Board Area  ............. 355.53 (mm)
Actual Route Area  ............. 355.53 (mm)

Placement Areas: Name             Available         Required          Required/Available
                 Entire Board     711.05 Sq. (mm)   271.76 Sq. (mm)   38.22 %

Pins  .......................... 29
Pins per Route Area  ........... 0.08 Pins/Sq. (mm)

Layers  ........................ 2
    Layer 1 is a signal layer
        Trace Widths  .......... 0.51
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... 0.51

Nets  .......................... 4
Connections  ................... 25
Open Connections  .............. 0
Differential Pairs  ............ 0
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 51.65 (mm)

Trace Widths Used (mm)  ........ 0.51
Vias  .......................... 10
Via Span  Name                   Quantity
   1-2    026VIA                 10

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 15
    Parts Mounted on Top  ...... 15
        SMD  ................... 10
        Through  ............... 5
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 20
    Holes per Board Area  ...... 0.06 Holes/Sq. (mm)
Mounting Holes  ................ 1

Wirebonds
    Bond Fingers ............... 0
    Bond Wires ................. 0