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xPCB Layout - Version 116.0.506.6156
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Job Directory:        E:\Compulab VX.2\FT.O-POW12-REV.1.1\PCB\

Design Status Report: E:\Compulab VX.2\FT.O-POW12-REV.1.1\PCB\LogFiles\DesignStatus_01.txt

Mon Mar 09 11:40:12 2020

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DESIGN STATUS
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Board Size Extents  ............ 13.649 X 26.384 (mm)
Route Border Extents  .......... 13.432 X 25.984 (mm)
Actual Board Area  ............. 355.527 (mm)
Actual Route Area  ............. 339.238 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    711.054 Sq. (mm)  271.761 Sq. (mm)  38.22 %

Pins  .......................... 29
Pins per Route Area  ........... 0.085 Pins/Sq. (mm)

Layers  ........................ 2
    Layer 1 is a signal layer
        Trace Widths  .......... 0.508
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.

Nets  .......................... 4
Connections  ................... 29
Open Connections  .............. 0
Differential Pairs  ............ 0
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 9.753 (mm)

Trace Widths Used (mm)  ........ 0.508
Vias  .......................... 5
Via Span  Name                   Quantity
   1-2    026VIA                 5

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 15
    Parts Mounted on Top  ...... 15
        SMD  ................... 10
        Through  ............... 5
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 15
    Holes per Board Area  ...... 0.042 Holes/Sq. (mm)
Mounting Holes  ................ 1

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0