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xPCB Layout - Version 116.0.506.6156
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Job Directory:        E:\Compulab VX.2\FT.O-POW12 rev 1.3\PCB\

Design Status Report: E:\Compulab VX.2\FT.O-POW12 rev 1.3\PCB\LogFiles\DesignStatus_04.txt

Mon Sep 21 07:59:36 2020

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DESIGN STATUS
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Board Size Extents  ............ 13.649 X 27.884 (mm)
Route Border Extents  .......... 13.432 X 26.881 (mm)
Actual Board Area  ............. 376.001 (mm)
Actual Route Area  ............. 334.781 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    752.002 Sq. (mm)  286.234 Sq. (mm)  38.06 %

Pins  .......................... 38
Pins per Route Area  ........... 0.114 Pins/Sq. (mm)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 0.152, 0.508
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        +12V_MAIN
        +V12
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 0.152

Nets  .......................... 5
Connections  ................... 43
Open Connections  .............. 0
Differential Pairs  ............ 0
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 12.674 (mm)

Trace Widths Used (mm)  ........ 0.152, 0.508
Vias  .......................... 28
Via Span  Name                   Quantity
   1-4    026VIA                 28

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 16
    Parts Mounted on Top  ...... 16
        SMD  ................... 11
        Through  ............... 5
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 38
    Holes per Board Area  ...... 0.101 Holes/Sq. (mm)
Mounting Holes  ................ 1

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0