
                               Forward Annotation
                               ------------------

                       07:25 AM Sunday, September 06, 2020
   Job Name: E:\Job\Compulab-VX2\FT.O-POW12 rev 1.3\PCB\FT.O-POW12-REV.1.3.pcb


Version:  01.01.00

     The PDBs listed in the project file will be searched to satisfy the parts
      requirements of the iCDB only for parts not already found in the
      Target PDB.

     The schematic source is a Keyin Netlist.
     

     Netlist has no syntax errors

     The Keyin Netlist has been read

     Target PDB Name: Work\Layout_Temp\PartsDB.pdb

     Number of Part Numbers: 9
          Part Numb: 131D76820S -> Vend Part: 131D76820S 
          Part Numb: 132D00150S -> Vend Part: 132D00150S 
          Part Numb: 147D30000S -> Vend Part: 147D30000S 
          Part Numb: 151C10611S -> Vend Part: 151C10611S 
          Part Numb: 151C22620S -> Vend Part: 151C22620S 
          Part Numb: 151D10510S -> Vend Part: 151D10510S 
          Part Numb: 161C00005S -> Vend Part: 161C00005S 
          Part Numb: 180K00202 -> Vend Part: 180K00202 
          Part Numb: 188Z01380 -> Vend Part: 188Z01380 

     Number of Part Names: 0

     Number of Part Labels: 0




     5 nets were found containing 36 pins
     16 components were found

     Creating a formatted Schematic Netlist (LogFiles\SchematicNetlist.txt)...
     A formatted Schematic Netlist has been created.

     The Logic DataBase and the Schematic Design are now in sync.  Use
      Netload to bring the Component Design into sync.

     Logic Data has been successfully Compiled with no errors or warnings.
      Please proceed with your component Design.
                                     NetLoad
                                     -------

                       07:26 AM Sunday, September 06, 2020
   Job Name: E:\Job\Compulab-VX2\FT.O-POW12 rev 1.3\PCB\FT.O-POW12-REV.1.3.pcb


Version:  02.11.12

	Netloading the Layout.  Unused components will be deleted.

	Unconnected pins will be set to net "(Net0)".

	Schematic reference designator changes will be forward annotated.


     Netload completed successfully with 0 warning(s).
     
     Back Annotating...

  Updating Logic Database...

     Version:  99.00.05

     Writing a list of routed plane pins to Logic\rtdplane.caf.

     Finished updating the Logic Database.

     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...
     A formatted Schematic Netlist has been created.

            Creating a new Keyin Netlist (E:\Job\Compulab-VX2\FT.O-POW12 rev 1.3\PCB\Logic\FT-O-POW12.kyn)
            from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
  A new Keyin Netlist has been generated.



                 Beginning Netload on the Layout Design.
           ---------------------------------------------------

Forward-Annotation on the Layout Design has been successfully completed.

There were 0 reassignments of nets.
There were 0 traces broken back.
There were 0 nets removed from the Layout Design.