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xPCB Planner - Version 116.0.506.6099
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Job Directory:        C:\Projects\Tensor\TELs\FT-SATA1\FT-SATA1 1_1\Layout\10_08\FT-SATA1 Rev1.1-100820\PCB\

Design Status Report: C:\Projects\Tensor\TELs\FT-SATA1\FT-SATA1 1_1\Layout\10_08\FT-SATA1 Rev1.1-100820\PCB\LogFiles\DesignStatus_05.txt

Mon Aug 10 15:21:15 2020

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DESIGN STATUS
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Board Size Extents  ............ 55.45 X 22.71 (mm)
Route Border Extents  .......... 54.45 X 21.71 (mm)
Actual Board Area  ............. 1,259.46 (mm)
Actual Route Area  ............. 1,182.29 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    2,518.91 Sq. (mm) 854.49 Sq. (mm)   33.92 %

Pins  .......................... 192
Pins per Route Area  ........... 0.16 Pins/Sq. (mm)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 0.1, 0.12, 0.12, 0.13, 0.2, 0.25, 0.3, 0.3, 0.46, 0.89
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 0.12, 0.12, 0.2, 0.46

Nets  .......................... 29
Connections  ................... 137
Open Connections  .............. 1
Differential Pairs  ............ 4
Differential Pair Names:   SATA_RXN   SATA_RXP
                           SATA_RXN_C   SATA_RXP_C
                           SATA_TXN   SATA_TXP
                           SATA_TXN_C   SATA_TXP_C
                           
Percent Routed  ................ 99.27 %

Netline Length  ................ 0.03 (mm)
Netline Manhattan Length  ...... 0.05 (mm)
Total Trace Length  ............ 355.39 (mm)

Trace Widths Used (mm)  ........ 0.1, 0.12, 0.12, 0.13, 0.2, 0.25, 0.3, 0.3, 0.46, 0.89
Vias  .......................... 72
Via Span  Name                   Quantity
   1-4    VIA8_pad18             14
          via20rd10              58

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 55
    Parts Mounted on Top  ...... 55
        SMD  ................... 42
        Through  ............... 3
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 84
    Holes per Board Area  ...... 0.07 Holes/Sq. (mm)
Mounting Holes  ................ 8
