=======================================================================
xPCB Layout - Version 116.0.506.6156
=======================================================================

Job Directory:        E:\Compulab VX.2\FT-SATA1 Rev1.1\PCB\

Design Status Report: E:\Compulab VX.2\FT-SATA1 Rev1.1\PCB\LogFiles\DesignStatus_07.txt

Tue Aug 11 18:53:04 2020

=======================================================================
DESIGN STATUS
=======================================================================
Board Size Extents  ............ 55.45 X 22.713 (mm)
Route Border Extents  .......... 54.45 X 21.713 (mm)
Actual Board Area  ............. 1,259.456 (mm)
Actual Route Area  ............. 1,182.293 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    2,518.913 Sq. (mm)854.489 Sq. (mm)  33.92 %

Pins  .......................... 192
Pins per Route Area  ........... 0.162 Pins/Sq. (mm)

Layers  ........................ 4
    Layer 1 is a signal layer
        Trace Widths  .......... 0.1, 0.117, 0.122, 0.127, 0.203, 0.25, 0.3, 0.305, 0.457, 0.889
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... 0.117, 0.122, 0.203, 0.457

Nets  .......................... 29
Connections  ................... 137
Open Connections  .............. 0
Differential Pairs  ............ 4
Differential Pair Names:   SATA_RXN   SATA_RXP
                           SATA_RXN_C   SATA_RXP_C
                           SATA_TXN   SATA_TXP
                           SATA_TXN_C   SATA_TXP_C
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (mm)
Netline Manhattan Length  ...... 0 (mm)
Total Trace Length  ............ 363.1 (mm)

Trace Widths Used (mm)  ........ 0.1, 0.117, 0.122, 0.127, 0.203, 0.25, 0.3, 0.305, 0.457, 0.889
Vias  .......................... 71
Via Span  Name                   Quantity
   1-4    VIA8_pad18             14
          via20rd10              57

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 55
    Parts Mounted on Top  ...... 55
        SMD  ................... 42
        Through  ............... 3
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 83
    Holes per Board Area  ...... 0.066 Holes/Sq. (mm)
Mounting Holes  ................ 8

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0