
                               Forward Annotation
                               ------------------

                        06:21 PM Tuesday, August 11, 2020
       Job Name: E:\Compulab VX.2\FT-SATA1 Rev1.1\PCB\FT-SATA1 Rev1.1.pcb


Version:  01.01.00

     The PDBs listed in the project file will be searched to satisfy the parts
      requirements of the iCDB only for parts not already found in the
      Target PDB.

     The schematic source is a Keyin Netlist.
     

     Netlist has no syntax errors

     The Keyin Netlist has been read

     Target PDB Name: Work\Layout_Temp\PartsDB.pdb

     Number of Part Numbers: 15
          Part Numb: 111S31000S -> Vend Part: 111S31000S 
          Part Numb: 131D03350S -> Vend Part: 131D03350S 
          Part Numb: 131D31540S -> Vend Part: 131D31540S 
          Part Numb: 131D41510S -> Vend Part: 131D41510S 
          Part Numb: 151B10600S -> Vend Part: 151B10600S 
          Part Numb: 151C10300S -> Vend Part: 151C10300S 
          Part Numb: 151C10400S -> Vend Part: 151C10400S 
          Part Numb: 151C22620S -> Vend Part: 151C22620S 
          Part Numb: 161C00005S -> Vend Part: 161C00005S 
          Part Numb: 161C10011S -> Vend Part: 161C10011S 
          Part Numb: 161C10021S -> Vend Part: 161C10021S 
          Part Numb: 161C20021S -> Vend Part: 161C20021S 
          Part Numb: 180K02201S -> Vend Part: 180K02201S 
          Part Numb: 182K06700S -> Vend Part: 182K06700S 
          Part Numb: 188Z01380 -> Vend Part: 188Z01380 

     Number of Part Names: 0

     Number of Part Labels: 0




     29 nets were found containing 157 pins
     45 components were found

     Creating a formatted Schematic Netlist (LogFiles\SchematicNetlist.txt)...
     A formatted Schematic Netlist has been created.

     The Logic DataBase and the Schematic Design are now in sync.  Use
      Netload to bring the Component Design into sync.

     Logic Data has been successfully Compiled with no errors or warnings.
      Please proceed with your component Design.
                                     NetLoad
                                     -------

                        06:21 PM Tuesday, August 11, 2020
       Job Name: E:\Compulab VX.2\FT-SATA1 Rev1.1\PCB\FT-SATA1 Rev1.1.pcb


Version:  02.11.12

	Netloading the Layout.  Unused components will be deleted.

	Unconnected pins will be set to net "(Net0)".

	Schematic reference designator changes will be forward annotated.


     Netload completed successfully with 0 warning(s).
     
     Back Annotating...

  Updating Logic Database...

     Version:  99.00.05

     Writing a list of routed plane pins to Logic\rtdplane.caf.

     Finished updating the Logic Database.

     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...
     A formatted Schematic Netlist has been created.

            Creating a new Keyin Netlist (E:\Compulab VX.2\FT-SATA1 Rev1.1\PCB\Logic\FT-SATA1-1_1.kyn)
            from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
  A new Keyin Netlist has been generated.



                 Beginning Netload on the Layout Design.
           ---------------------------------------------------

Forward-Annotation on the Layout Design has been successfully completed.

There were 0 reassignments of nets.
There were 0 traces broken back.
There were 0 nets removed from the Layout Design.