
                                Circuit Paste log
                                -----------------

                       12:15 PM Monday, November 02, 2020
        Job Name: D:\Compulab VX.2\FT-POE2-rev1.1\PCB\FT-POE2-rev1.1.pcb

         Clipboard: C:\Users\Itzik\AppData\Local\Temp\mgc_icc_clipboard\Layout\
    


Checking Ref Des Map
--------------------

Checking Ref Des Map completed
    Map is OK


Checking Netlist Mapping (using schematic circuit definitions)
--------------------------------------------------------------

Checking Netlist Map completed
    0 Error(s) fixed

Updating Local Libraries
------------------------

Library update is not required


Loading Padstacks
-----------------

0 Padstacks were created


Synthesizing EP Components
--------------------------

EP Component synthesizing is completed
    0 Components are synthesized


Placing Components
------------------

Component placement complete
    0 Components were placed


Loading net items
-----------------

Loading of Net items complete
    9 objects were created
        1 plane shapes
        8 traces


Loading Fiducials
-----------------

Fiducial loading completed
    0 fiducials are created


Loading spacers
---------------

Loading spacers complete
    0 objects were created


Loading Texts
-------------

Text loading complete
    0 texts were created


Loading Drawings
----------------

Drawing loading completed
    0 drawings were created


Loading Dimension Data
----------------------

Dimension Data loading completed
    0 dimensions were created
