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xPCB Layout - Version 116.0.506.6156
=======================================================================

Job Directory:        E:\Compulab VX.2\FT.N-PCIEx16\PCB\

Design Status Report: E:\Compulab VX.2\FT.N-PCIEx16\PCB\LogFiles\DesignStatus_01.txt

Wed Mar 18 08:47:33 2020

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DESIGN STATUS
=======================================================================
Board Size Extents  ............ 4.154 X 0.728 (in)
Route Border Extents  .......... 4.114 X 0.689 (in)
Actual Board Area  ............. 3.025 (in)
Actual Route Area  ............. 2.835 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    6.05 Sq. (in)     2.867 Sq. (in)    47.38 %

Pins  .......................... 633
Pins per Route Area  ........... 223.314 Pins/Sq. (in)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 4.5, 5, 12, 20
    Layer 2 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 3 is a Positive Plane Layer with nets
        +5VA
        Trace Widths  .......... None.
    Layer 4 is a Positive Plane Layer with nets
        +3V3S
        Trace Widths  .......... None.
    Layer 5 is a Positive Plane Layer with nets
        GND
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 4.5, 5, 8, 12, 15, 20

Nets  .......................... 123
Connections  ................... 425
Open Connections  .............. 0
Differential Pairs  ............ 49
Differential Pair Names:   CLK_PCIE_13N   CLK_PCIE_13P
                           PEG_RXN0   PEG_RXP0
                           PEG_RXN1   PEG_RXP1
                           PEG_RXN2   PEG_RXP2
                           PEG_RXN3   PEG_RXP3
                           PEG_RXN4   PEG_RXP4
                           PEG_RXN5   PEG_RXP5
                           PEG_RXN6   PEG_RXP6
                           PEG_RXN7   PEG_RXP7
                           PEG_RXN8   PEG_RXP8
                           PEG_RXN9   PEG_RXP9
                           PEG_RXN10   PEG_RXP10
                           PEG_RXN11   PEG_RXP11
                           PEG_RXN12   PEG_RXP12
                           PEG_RXN13   PEG_RXP13
                           PEG_RXN14   PEG_RXP14
                           PEG_RXN15   PEG_RXP15
                           PEG_TXN0   PEG_TXP0
                           PEG_TXN0_C   PEG_TXP0_C
                           PEG_TXN1   PEG_TXP1
                           PEG_TXN1_C   PEG_TXP1_C
                           PEG_TXN2   PEG_TXP2
                           PEG_TXN2_C   PEG_TXP2_C
                           PEG_TXN3   PEG_TXP3
                           PEG_TXN3_C   PEG_TXP3_C
                           PEG_TXN4   PEG_TXP4
                           PEG_TXN4_C   PEG_TXP4_C
                           PEG_TXN5   PEG_TXP5
                           PEG_TXN5_C   PEG_TXP5_C
                           PEG_TXN6   PEG_TXP6
                           PEG_TXN6_C   PEG_TXP6_C
                           PEG_TXN7   PEG_TXP7
                           PEG_TXN7_C   PEG_TXP7_C
                           PEG_TXN8   PEG_TXP8
                           PEG_TXN8_C   PEG_TXP8_C
                           PEG_TXN9   PEG_TXP9
                           PEG_TXN9_C   PEG_TXP9_C
                           PEG_TXN10   PEG_TXP10
                           PEG_TXN10_C   PEG_TXP10_C
                           PEG_TXN11   PEG_TXP11
                           PEG_TXN11_C   PEG_TXP11_C
                           PEG_TXN12   PEG_TXP12
                           PEG_TXN12_C   PEG_TXP12_C
                           PEG_TXN13   PEG_TXP13
                           PEG_TXN13_C   PEG_TXP13_C
                           PEG_TXN14   PEG_TXP14
                           PEG_TXN14_C   PEG_TXP14_C
                           PEG_TXN15   PEG_TXP15
                           PEG_TXN15_C   PEG_TXP15_C
                           
Percent Routed  ................ 100.00 %

Netline Length  ................ 0 (in)
Netline Manhattan Length  ...... 0 (in)
Total Trace Length  ............ 63.011 (in)

Trace Widths Used (th)  ........ 4.5, 5, 8, 12, 15, 20
Vias  .......................... 340
Via Span  Name                   Quantity
   1-6    VIA8_pad18             340

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 108
    Parts Mounted on Top  ...... 25
        SMD  ................... 13
        Through  ............... 2
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 83
        SMD  ................... 83
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 362
    Holes per Board Area  ...... 119.661 Holes/Sq. (in)
Mounting Holes  ................ 20

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0