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xPCB Layout - Version 116.0.506.6156
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Job Directory:        E:\Compulab VX.2\FT.W-OPLN2\PCB\

Design Status Report: E:\Compulab VX.2\FT.W-OPLN2\PCB\LogFiles\DesignStatus_02.txt

Mon May 31 10:29:17 2021

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DESIGN STATUS
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Board Size Extents  ............ 44.4 X 72.961 (mm)
Route Border Extents  .......... 43.4 X 71.953 (mm)
Actual Board Area  ............. 3,107.09 (mm)
Actual Route Area  ............. 2,986.108 (mm)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    6,214.179 Sq. (mm)2,429.71 Sq. (mm) 39.10 %

Pins  .......................... 717
Pins per Route Area  ........... 0.24 Pins/Sq. (mm)

Layers  ........................ 6
    Layer 1 is a signal layer
        Trace Widths  .......... 0.089, 0.114, 0.119, 0.254, 0.305, 0.508, 1.27
    Layer 2 is a Positive Plane Layer with nets
        GND
        CHASSIS
        Trace Widths  .......... 0.089, 0.114, 0.119, 0.254, 0.305
    Layer 3 is a signal layer
        Trace Widths  .......... 0.081, 0.089, 0.254
    Layer 4 is a signal layer
        Trace Widths  .......... None.
    Layer 5 is a Positive Plane Layer with nets
        GND
        CHASSIS
        Trace Widths  .......... 0.089, 0.114, 0.119, 0.254, 0.305
    Layer 6 is a signal layer
        Trace Widths  .......... 0.089, 0.114, 0.119, 0.127, 0.254, 0.305, 0.508, 1.27

Nets  .......................... 149
Connections  ................... 548
Open Connections  .............. 1
Differential Pairs  ............ 15
Differential Pair Names:   CLK_PCIE_N   CLK_PCIE_P
                           CLK_PCIE_0N   CLK_PCIE_0P
                           CLK_PCIE_0N_R   CLK_PCIE_0P_R
                           CLK_PCIE_1N   CLK_PCIE_1P
                           CLK_PCIE_1N_R   CLK_PCIE_1P_R
                           LAN_SER_N   LAN_SER_P
                           LAN_SER_N_2   LAN_SER_P_2
                           LAN_SET_N   LAN_SET_P
                           LAN_SET_N_2   LAN_SET_P_2
                           PCIE0_RXN   PCIE0_RXP
                           PCIE0_RXN_C   PCIE0_RXP_C
                           PCIE0_TXN   PCIE0_TXP
                           PCIE1_RXN   PCIE1_RXP
                           PCIE1_RXN_C   PCIE1_RXP_C
                           PCIE1_TXN   PCIE1_TXP
                           
Percent Routed  ................ 99.82 %

Netline Length  ................ 0.023 (mm)
Netline Manhattan Length  ...... 0.028 (mm)
Total Trace Length  ............ 1,621.945 (mm)

Trace Widths Used (mm)  ........ 0.081, 0.089, 0.114, 0.119, 0.127, 0.254, 0.305, 0.508, 1.27
Vias  .......................... 629
Via Span  Name                   Quantity
   1-6    VIA8_pad18             96
   1-2    uVIA4_pad10            151
   2-3    uVIA4_pad10            24
   2-5    VIA8_pad18             188
   4-5    uVIA4_pad10            21
   5-6    uVIA4_pad10            149

Teardrops....................... 0
    Pad Teardrops............... 0
    Trace Teardrops............. 0
    Custom Teardrops............ 0
Tracedrops...................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 208
    Parts Mounted on Top  ...... 98
        SMD  ................... 84
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 10
    Parts Mounted on Bottom  ... 110
        SMD  ................... 110
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Embedded Components ........ 0
        Capacitors ............. 0
        Resistors .............. 0
    RF Shapes .................. 0

    Edge Connector Parts  ...... 0

Parts not Placed  .............. 0

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 144
    Holes per Board Area  ...... 0.046 Holes/Sq. (mm)
Mounting Holes  ................ 8

Wirebonds
    Bondpads ................... 0
    Bond Wires ................. 0